One type of memory known in the art is Dynamic Random Access Memory (DRAM). One type of DRAM is Pseudo Static Random Access Memory (PSRAM). PSRAM is a low power DRAM having a Static Random Access Memory (SRAM) interface for wireless applications. In general, DRAM includes at least one array of memory cells. The memory cells in the array of memory cells are arranged in rows and columns, with the rows extending along an x-direction and the columns extending along a y-direction. Conductive word lines extend across the array of memory cells along the x-direction and conductive bit lines extend across the array of memory cells along the y-direction. A memory cell is located at each cross point of a word line and a bit line. Memory cells are accessed using a row address and a column address.
DRAM uses a main clock signal and a data strobe signal (DQS) for addressing the array of memory cells and for executing commands within the memory. The clock signal is used as a reference for the timing of commands such as read and write operations, including address and control signals. The DQS signal is used as a reference to latch input data into the memory and output data into an external device.
A Column Address Strobe (CAS) signal is used to latch in the Column Addresses (CADD) for selected memory cells and initiate a column access during a read or write operation. Typically, the column addresses are latched and passed for decoding on the rising edge of the CAS signal. Therefore, any address set up time (i.e., the time the addresses are valid before the CAS signal rises) is wasted. The CAS signal, which functions as a clock for the column path, must not initiate a column access before the column addresses are latched and decoded. Initiating a column access before the column addresses are latched and decoded can cause several problems, such as the activation of an incorrect column element, which in turn would result in reading incorrect data. To prevent reading incorrect data, the CAS signal is typically delayed in the column path until the addresses are latched and decoded and have performed the necessary logic switches in the column. Delaying the CAS signal in the column path slows down read and write accesses to the memory.